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S2060C bảng dữ liệu(PDF) 1 Page - Applied Micro Circuits Corporation |
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S2060C bảng dữ liệu(HTML) 1 Page - Applied Micro Circuits Corporation |
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1 / 22 page ![]() 1 S2060 GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision H S2060 ® DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER FEATURES • Operating rate • 1250 MHz (Gigabit Ethernet) line rates • Half and full VCO output rates • Functionally compliant IEEE 802.3z Gigabit Ethernet standard • Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference • Receiver PLL provides clock and data recovery • 10-bit parallel TTL compatible interface • Low-jitter serial LVPECL compatible interface • Local loopback • Single +3.3 V supply, 620 mW power dissipation • 64 PQFP or TQFP package • Continuous downstream clocking from receiver • Drives 30 m of Twinax cable directly APPLICATIONS • Workstation • Frame buffer • Switched networks • Data broadcast environments • Proprietary extended backplanes GENERAL DESCRIPTION The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber op- tic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word. The chip provides parallel-to-serial and serial-to-par- allel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a low- speed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fi- ber optic component interfaces with excellent signal integrity. Local loopback mode allows for system di- agnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW. The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip. Figure 1. System Block Diagram S2060 Gigabit Ethernet Controller Optical Tx Optical Rx Optical Tx Optical Rx S2060 Gigabit Ethernet Controller |
Số phần tương tự - S2060C |
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Mô tả tương tự - S2060C |
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