OBSOLETE

CLC409

SNOS853E – AUGUST 2000 – REVISED APRIL 2013

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The two input bias currents are physically unrelated in both magnitude and polarity for the current feedback

topology. It is not possible, therefore, to cancel their effects by matching the source impedance for the two inputs

(as is commonly done for matched input bias current devices).

The total output noise is computed in a similar fashion to output offset voltage. Using the input noise voltage and

two input noise currents, the output noise is developed through the same gain equations for each term but

combined as the square root of the sum of squared contributing elements. See Application Note OA-12 for a full

discussion of noise calculations for current feedback amplifiers.

Printed Circuit Layout

As with any high speed component, a careful attention to the board layout is necessary for optimum

performance. Evaluation PC boards (CLC730013-DIP, CLC730027-SOIC, and CLC730068-SOT) for the CLC409

Further layout suggestions can be found in Application Note OA-15.

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