ATMEGA323L-4AI datasheet(77/247 Pages) ATMEL

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ATmega323(L)

1457G–AVR–09/03

Table 29 contains equations for calculating the baud rate (in bits per second) and for

calculating the UBRR value for each mode of operation using an internally generated

clock source.

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps).

BAUD

Baud rate (in bits per second, bps)

fOSC

System Oscillator clock frequency

UBRR

Contents of the UBRRH and UBRRL Registers, (0 - 4095)

Some examples of UBRR values for some system clock frequency are found in Table

36 (see page 99).

Double Speed Operation

(U2X)

The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only

has effect for the asynchronous operation. Set this bit to zero when using synchronous

operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively

doubling the transfer rate for asynchronous communication. Note however that the

Receiver will in this case only use half the number of samples (reduced from 16 to 8) for

data sampling and clock recovery, and therefore a more accurate baud rate setting and

system clock are required when this mode is used. For the Transmitter, there are no

downsides.

External Clock

External clocking is used by the Synchronous Slave modes of operation. The descrip-

tion in this section refers to Figure 46 for details.

External clock input from the XCK pin is sampled by a synchronization register to mini-

mize the chance of meta-stability. The output from the synchronization register must

then pass through an edge detector before it can be used by the Transmitter and

Receiver. This process introduces a two CPU clock period delay and therefore the max-

imum external XCK clock frequency is limited by the following equation:

Note that fosc depends on the stability of the system clock source. It is therefore recom-

mended to add some margin to avoid possible loss of data due to frequency variations.

Synchronous Clock Operation

When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock

input (Slave) or clock output (Master). The dependency between the clock edges and

data sampling or data change is the same. The basic principle is that data input (on

RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is

changed.

Table 29. Equations for Calculating Baud Rate Register Setting

Operating Mode

Equation for Calculating

Baud Rate(1)

Equation for Calculating

UBRR Value

Asynchronous Normal Mode

(U2X = 0)

Asynchronous Double Speed

Mode (U2X = 1)

Synchronous Master Mode

BAUD

OSC

16 UBRR

()

----------------------------------------

UBRR

OSC

16BAUD

------------------------

–

BAUD

OSC

8 UBRR

()

------------------------------------

UBRR

OSC

8BAUD

---------------------1

–

BAUD

OSC

2 UBRR

()

------------------------------------

UBRR

OSC

2BAUD

---------------------1

–

XCK

OS C

-----------

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