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VRG8692 bảng dữ liệu(PDF) 7 Page - Aeroflex Circuit Technology |
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VRG8692 bảng dữ liệu(HTML) 7 Page - Aeroflex Circuit Technology |
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7 / 10 page ![]() SCD8691 Rev H 11/12/13 Aeroflex Plainview 7 FIGURE 6 – SLOW START VRG8691/92 VIN VOUT VSENSE CURR. LIMIT 10 11 12 4 3 2 1 8 ENABLE 6 9 7 5 0.1µF 47µF + VBIAS SLOW START VBIAS VIN GND 0.1µF 0 CSS + ENABLE If it is desirable to control the output rise time, a capacitor (CSS) can be asserted on the Slow Start pin to adjust the rise time for the following: A. Large load capacitance will cause high surge currents which will trip the current limit circuitry. The use of CSS will allow the output voltage to rise slowly thus mitigate the surge current phenomenon. B. CSS may be used solely to control VOUT RISE TIME (Tr), when CLOAD is not an issue. C. CSS is effective only when VIN is applied prior to VBIAS or ENABLE. > CSS CLOAD (0.4 X 0.0014) X VOUT NOM ICL - ILOAD NOM Note: CSS in Farads and TR in seconds. TR = CSS X 2.5 0.0014 () APPLICATION NOTE 4 VOUT START UP RISE TIME CONTROL Utilizing the Slow Start option: When the VRG8691/92 is first powered up, using the Slow Start function controls the rate at which VOUT rises to the required voltage set by R1 and R2. Note: VIN should be applied before VBIAS when the Slow Start feature is used. R1 R2 VREF (=1V) IADJ CLOAD 47µF VOUT + TANT 1µF 1µF TANT CER CER |
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