UT54ACTS163 datasheet(2/10 Pages) AEROFLEX

tên linh kiện	UT54ACTS163

Giải thích chi tiết về linh kiện	4-Bit Synchronous Counters

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FUNCTION TABLE

H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition

L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition

Notes:

1. The RCO output is high when ENT is high and the counter is at terminal count HHHH.

2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations.

3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations.

LOGIC DIAGRAM

Operating Mode

CLR

CLK

ENP

ENT

LOAD

DATA A,B,C,D

RCO

Reset (Clear)

↑

Parallel Load

↑

Count

↑

Count

Inhibit

l 2

(2)

(1)

(9)

(7)

(10)

(3)

(4)

(5)

(6)

(14)

(12)

(13)

(11)

(15)

RCO

DATA D

DATA C

DATA B

DATA A

ENT

ENP

LOAD

CLR

CLK

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