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DRV8843PWPR bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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DRV8843PWPR bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 28 page ![]() DRV8843 www.ti.com SLVSAS8D – APRIL 2011 – REVISED NOVEMBER 2015 7.4.6 Protection Circuits The DRV8843 is fully protected against undervoltage, overcurrent and overtemperature events. 7.4.6.1 Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is removed and re-applied. Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage. 7.4.6.2 Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. 7.4.6.3 Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: DRV8843 |
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