SAB80C166W datasheet(21/67 Pages) INFINEON

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SAB 80C166W/83C166W

Semiconductor Group

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to

prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time

interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up

procedure is always monitored. The software has to be designed to service the Watchdog Timer

before it overflows. If, due to hardware or software related failures, the software fails to do so, the

Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low

in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. The

high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in

WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced

by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals

between 25

µs and 420 ms can be monitored (@ 20 MHz CPU clock). The default Watchdog Timer

interval after reset is 6.55 ms (@ 20 MHz CPU clock).

Bootstrap Loader

The SAB 80C166W/83C166W provides a built-in bootstrap loader (BSL), which allows to start

program execution out of the SAB 80C166W/83C166W’s internal RAM. This start program is

loaded via the serial interface ASC0 and does not require external memory or an internal ROM.

The SAB 80C166W/83C166W enters BSL mode, when ALE is sampled high at the end of a

hardware reset and if NMI becomes active directly after the end of the internal reset sequence. BSL

mode is entered independent of the bus mode selected via EBC0, EBC1 and BUSACT.

After entering BSL mode the SAB 80C166W/83C166W scans the RXD0 line to receive a zero byte,

ie. one start bit, eight ‘0’ data bits and one stop bit. From the duration of this zero byte it calculates

the corresponding baudrate factor with respect to the current CPU clock and initializes ASC0

accordingly. Using this baudrate, an acknowledge byte is returned to the host that provides the

loaded data. The SAB 80C166W/83C166W returns the value <55H>.

The next 32 bytes received via ASC0 are stored sequentially into locations 0FA40H through

0FA5FH of the internal RAM. To execute the loaded code the BSL then jumps to location 0FA40H.

The loaded program may load additional code / data, change modes, etc.

The SAB 80C166W/83C166W exits BSL mode upon a software reset (ignores the ALE level) or a

hardware reset (remove conditions for entering BSL mode before).

Instruction Set Summary

The summary on the following pages lists the instructions of the SAB 80C166W/83C166W ordered

into logical groups.

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