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SAB80C166 bảng dữ liệu(PDF) 48 Page - Infineon Technologies AG |
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SAB80C166 bảng dữ liệu(HTML) 48 Page - Infineon Technologies AG |
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48 / 52 page ![]() SAB 80C166/83C166 Semiconductor Group 47 AC Characteristics (cont’d) CLKOUT and READY V CC = 5 V ± 10 %; V SS = 0 V T A = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M T A = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 C L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Notes 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. CLKOUT cycle time t29 CC 50 50 2TCL 2TCL ns CLKOUT high time t30 CC 20 – TCL – 5 – ns CLKOUT low time t31 CC 15 – TCL – 10 – ns CLKOUT rise time t32 CC – 5 –5ns CLKOUT fall time t33 CC – 5 –5ns CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + tA ns Synchronous READY setup time to CLKOUT t35 SR 10 – 10 – ns Synchronous READY hold time after CLKOUT t36 SR 10 – 10 – ns Asynchronous READY low time t37 SR 65 – 2TCL + 15 – ns Asynchronous READY setup time 1) t58 SR 20 – 20 – ns Asynchronous READY hold time 1) t59 SR 0 – 0–ns Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60 SR 0 0 + 2tA + tF 2) 0 TCL - 25 + 2tA + tF 2) ns |
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