ACE25C200G datasheet(35/48 Pages) ACE

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ACE25C200G

2M BIT SPI NOR FLASH

VER 1.1

32KB Block Erase (52H)

The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable

instruction must previously have been executed to set the Write Enable Latch bit. The 32KB Block

Erase instruction is entered by driving /CS low, followed by the instruction code, and three address

bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase instruction.

/CS must be driven low for the entire duration of the sequence.

See Figure 27, the 32KB Block Erase instruction sequence: /CS goes low sending 32KB Block

Erase instruction 3-byte address on SI /CS goes high. The instruction sequence is shown in Figure19.

/CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the

32KB Block Erase instruction is not executed. As soon as /CS is driven high, the self-timed Block

Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status

(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some

unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 32KB Block

Erase instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0)

bits (see Table 6 & 7)

is not executed.

Figure 27 32KB Block Erase Sequence Diagram

Figure 27

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