công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

PEF2256 bảng dữ liệu(PDF) 54 Page - Infineon Technologies AG

tên linh kiện PEF2256
Giải thích chi tiết về linh kiện  E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
PDF  518 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  INFINEON [Infineon Technologies AG]
Trang chủ  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEF2256 bảng dữ liệu(HTML) 54 Page - Infineon Technologies AG

Back Button PEF2256 Datasheet HTML 50Page - Infineon Technologies AG PEF2256 Datasheet HTML 51Page - Infineon Technologies AG PEF2256 Datasheet HTML 52Page - Infineon Technologies AG PEF2256 Datasheet HTML 53Page - Infineon Technologies AG PEF2256 Datasheet HTML 54Page - Infineon Technologies AG PEF2256 Datasheet HTML 55Page - Infineon Technologies AG PEF2256 Datasheet HTML 56Page - Infineon Technologies AG PEF2256 Datasheet HTML 57Page - Infineon Technologies AG PEF2256 Datasheet HTML 58Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 54 / 518 page
background image
FALC
®56
PEF 2256 H/E
Functional Description E1/T1/J1
User’s Manual
54
DS1.1, 2003-10-23
Hardware Description
3.3.1.3
Interrupt Interface
Special events in the FALC
®56 are indicated by means of a single interrupt output with
programmable characteristics (open drain or push-pull, defined by register IPC), which
requests the CPU to read status information from the FALC
®56, or to transfer data
from/to the FALC
®56.
Since only one INT request output is provided, the cause of an interrupt must be
determined by the CPU by reading the FALC
®56’s interrupt status registers (GIS,
ISR(5:0)). The interrupt on pin INT and the interrupt status bits are reset by reading the
interrupt status registers. Register ISR(5:0) are of type “clear on read“.
The structure of the interrupt status registers is shown in Figure 8.
Figure 8
Interrupt Status Registers
Each interrupt indication of registers ISR(5:0) can be selectively masked by setting the
according bit in the corresponding mask registers IMR(5:0). If the interrupt status bits are
masked they neither generate an interrupt at INT nor are they visible in ISR(5:0).
GIS, the non-maskable Global Interrupt Status Register, serves as pointer to pending
interrupts. After the FALC
®56 has requested an interrupt by activating its INT pin, the
CPU should first read the Global Interrupt Status register GIS to identify the requesting
IMR0
F0127 V1.0
Global
Interrupt
Status
Register GIS
ISR0
ISR0
ISR1
ISR2
ISR3
ISR4
ISR5
IMR1
ISR1
IMR2
ISR2
IMR3
ISR3
IMR4
ISR4
IMR5
ISR5



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com