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STM32F479AI bảng dữ liệu(PDF) 168 Page - STMicroelectronics

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Electrical characteristics
STM32F479xx
168/208
DocID028010 Rev 2
Synchronous waveforms and timings
Figures 61 through 64 represent synchronous waveforms and Table 97 through Table 100
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
BurstAccessMode = FMC_BurstAccessMode_Enable;
MemoryType = FMC_MemoryType_CRAM;
WriteBurst = FMC_WriteBurst_Enable;
CLKDivision = 1;
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period:
For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 90 MHz at CL = 30 pF (on FMC_CLK).
For 1.71 V≤ VDD<1.9 V, maximum FMC_CLK = 60 MHz at CL = 10 pF (on FMC_CLK).
Table 96. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
1. Based on test during characterization.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9THCLK
9THCLK+0.5
ns
tw(NWE)
FMC_NWE low time
7THCLK
7THCLK+2
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
6THCLK+1.5
-
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid
4THCLK–1
-



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