STM32F479AI datasheet(153/208 Pages) STMICROELECTRONICS

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DocID028010 Rev 2

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STM32F479xx

Electrical characteristics

187

Equation 1: RAIN max formula

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of

sampling periods defined in the ADC_SMPR1 register.

tCONV(2)

Total conversion time

(including sampling time)

fADC = 30 MHz

12-bit resolution

0.50

16.40

µs

fADC = 30 MHz

10-bit resolution

0.43

16.34

fADC = 30 MHz

8-bit resolution

0.37

16.27

fADC = 30 MHz

6-bit resolution

0.30

16.20

9 to 492

(tS for sampling +n-bit resolution for successive approximation)

1/fADC

fS(2)

Sampling rate

(fADC = 30 MHz, and

tS = 3 ADC cycles)

12-bit resolution

Single ADC

Msps

12-bit resolution

Interleave Dual ADC

mode

3.75

12-bit resolution

Interleave Triple ADC

mode

IVREF+(2)

ADC VREF

DC current consumption in

conversion mode

300

500

µA

IVDDA(2)

ADC VDDA

DC current consumption in

conversion mode

1.6

1.8

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).

2. Based on test during characterization.

3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.

5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 77.

Table 77. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RAIN

k0.5

–

()

fADC

CADC

()

---------------------------------------------------------------- R

ADC

–

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