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STAP16DPS05 bảng dữ liệu(PDF) 9 Page - STMicroelectronics

tên linh kiện STAP16DPS05
Giải thích chi tiết về linh kiện  Low voltage 16-bit constant current LED sink driver
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STAP16DPS05
Electrical characteristics
34
3.1
Switching characteristics
VDD = 5 V, Tj = 25 °C, unless otherwise specified.
Table 8. Switching characteristics (1)(2)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
fclk
Clock frequency
Cascade operation
30
MHz
tPLH1
CLK-OUTn
LE\DM1 = H
OE\DM2 = L
Propagation
delay time
(“L” to “H”)
VIH = VDD
VIL = GND
CL = 10 pF
Io = 20 mA
VL = 3 V
Rext = 1 KΩ
RL = 60
Ω
VDD= 3.3 V
40
45
ns
VDD = 5 V
20
45
tPLH2
LE\DM1-OUTn
OE\DM2 = L
VDD = 3.3 V
51
80
ns
VDD = 5 V
32
50
tPLH3
OE\DM2-OUTn
LE\DM1 = H
VDD = 3.3 V
50
80
ns
VDD = 5 V
30
50
tPLH
CLK - SDO
VDD = 3.3 V
22
35
ns
VDD = 5 V
15
25
tPHL1
CLK-OUTn
LE\DM1 = H
OE\DM2 = L
Propagation
delay time
(“H” to “L”)
VDD = 3.3 V
15
25
ns
VDD = 5 V
12
20
tPHL2
LE\DM1-OUTn
OE\DM2 = L
VDD = 3.3 V
13
25
ns
VDD = 5 V
10
15
tPHL3
OE\DM2-OUTn
LE\DM1 = H
VDD = 3.3 V
12
20
ns
VDD = 5 V
10
15
tPHL
CLK - SDO
VDD = 3.3 V
25
40
ns
VDD = 5 V
18
25
tON
Output rise time
10~90 % of voltage
waveform
VDD = 3.3 V
35
55
ns
VDD = 5 V
10
20
tOFF
Output fall time
90~10 % of voltage
waveform
VDD = 3.3 V
4
10
ns
VDD = 5 V
3
8
tr
CLK rise time(3)
5
µs
tf
CLK fall time(3)
5
1.
All table limits are guaranteed by design.
2.
Not tested in production.
3.
If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer
between two cascaded devices.



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