TUSB4041IPAPR datasheet(10/44 Pages) TI1

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td2

GRSTz

VDD33

VDD

MISC_IO

td1

tsu_io

thd_io

TUSB4041I

SLLSEK3B – JULY 2015 – REVISED DECEMBER 2015

www.ti.com

7.6 Power-Up Timing Requirements

MIN

NOM

MAX

UNIT

td1

VDD33 stable before VDD stable(1)

See (2)

td2

VDD and VDD33 stable before deassertion of GRSTz

tsu_io

Setup for MISC inputs(3) sampled at the deassertion of GRSTz

0.1

µs

thd_io

Hold for MISC inputs(3) sampled at the deassertion of GRSTz

0.1

µs

tVDD33_RAMP

VDD33 supply ramp requirements

0.2

100

tVDD_RAMP

VDD supply ramp requirements

0.2

100

(1)

An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay

counting from both power supplies being stable to the de-assertion of GRSTz.

(2)

The VDD33 and VDD have no power-on relationship unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable

minimum of 10

μs before the VDD33.

(3)

MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

Figure 1. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at TA = 25°C

VDD33

VDD

PARAMETER

UNIT

3.3 V

1.1 V

LOW POWER MODES

Power on (after reset)

2.3

Upstream disconnect

2.3

Suspend

2.5

ACTIVE MODES (US STATE AND DS STATE)

2.0 host / 1 HS device

2.0 host / 4 HS devices

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