SAF-C164CL datasheet(16/79 Pages) INFINEON

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C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Memory Organization

The memory space of the C164CI is configured in a Von Neumann architecture which

means that code memory, data memory, registers and I/O ports are organized within the

same linear address space which includes 16 MBytes. The entire memory space can be

accessed bytewise or wordwise. Particular portions of the on-chip memory have

additionally been made directly bitaddressable.

The C164CI incorporates 64 KBytes of on-chip OTP memory or 64/48 KBytes of on-chip

mask-programmable ROM (not in the ROM-less derivative, of course) for code or

constant data. The lower 32 KBytes of the on-chip ROM/OTP can be mapped either to

segment 0 or segment 1.

The OTP memory can be programmed by the CPU itself (in system, e.g. during booting)

or directly via an external interface (e.g. before assembly). The programming time is

approx. 100

µs per word. An external programming voltage VPP =11.5 V must be

supplied for this purpose (via pin EA/

VPP).

2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined

variables, for the system stack, general purpose register banks and even for code. A

…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2

× 512 bytes) of the address space are reserved for the Special Function

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user

stacks, or code. The XRAM is accessed like external memory and therefore cannot be

used for the system stack or for register banks and is not bitaddressable. The XRAM

permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the

microcontroller.

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