STM32F756VG datasheet(160/228 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F756xx

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DocID027589 Rev 4

Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate

function characteristics (CK, SD, WS).

Note:

Refer to RM0385 reference manual I2S section for more details on the sampling frequency

(FS).

fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these

parameters might be slightly impacted by the source clock precision. DCK depends mainly

on the value of ODD bit. The digital contribution leads to a minimum value of

(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS

maximum value is supported for each mode/condition.

Table 77. I2S dynamic characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

I2S Main clock output

256x8K

256xFs(2)

MHz

fCK

I2S clock frequency

Master data: 32 bits

64xFs

MHz

Slave data: 32 bits

64xFs

DCK

I2S clock frequency duty cycle Slave receiver

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

PCM short pulse mode(3)

th(WS)

WS hold time

Slave mode

PCM short pulse mode(3)

tsu(SD_MR)

Data input setup time

Master receiver

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

1.5

tv(SD_ST)

Data output valid time

Slave transmitter (after enable edge)

tv(SD_MT)

Master transmitter (after enable edge)

3.5

th(SD_ST)

Data output hold time

Slave transmitter (after enable edge)

th(SD_MT)

Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).

3. Measurement done with respect to I2S_CK rising edge.

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