M34E04B datasheet(13/35 Pages) STMICROELECTRONICS

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DocID028428 Rev 1

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M34E04B

Device operation

The device responds to the address byte with an acknowledge bit, and then waits for the

data byte.

When the bus master generates a Stop condition immediately after a data byte Ack bit (in

the “10th bit” time slot), either at the end of a Byte write or a Page write, the internal memory

Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal

Write cycle.

During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and

the device does not respond to any requests.

3.6.1

Byte write

After the device select code and the address byte, the bus master sends one data byte. The

device replies with Ack. The bus master terminates the transfer by generating a Stop

condition, as shown in Figure 5.

Figure 5. Write mode sequences in a non write-protected area

3.6.2

Page write

The Page write mode allows up to 16 bytes to be written in a single Write cycle, provided

that they are all located in the same page in the memory: that is, the most significant

memory address bits are the same. If more bytes are sent than will fit up to the end of the

page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to

become overwritten in an implementation dependent way.

The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the

device. After each byte is transferred, the internal byte address counter (the 4 least

significant address bits only) is incremented. The transfer is terminated by the bus master

generating a Stop condition.

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