HD3SS214

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SLAS907 – DECEMBER 2015

Layout Guidelines (continued)

11.1.2 Differential Traces

Guidelines for routing PCB traces are necessary when trying to maintain signal integrity and lower EMI. Although

there seems to be an endless number of precautions to be taken, this section provides only a few main

recommendations as layout guidance.

1. Reduce intra-pair skew in a differential trace by introducing small meandering corrections at the point of

mismatch.

2. Reduce inter-pair skew, caused by component placement and IC pinouts, by making larger meandering

correction along the signal path. Use chamfered corners with a length-to-trace width ratio of between 3 and

5. The distance between bends should be 8 to 10 times the trace width.

3. Use 45 degree bends (chamfered corners), instead of right-angle (90°) bends. Right-angle bends increase

the effective trace width, which changes the differential trace impedance creating large discontinuities. A 45o

bends is seen as a smaller discontinuity.

4. When routing around an object, route both trace of a pair in parallel. Splitting the traces changes the line-to-

line spacing, thus causing the differential impedance to change and discontinuities to occur.

5. Place passive components within the signal path, such as source-matching resistors or ac-coupling

capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b), the resulting

discontinuity, however, is limited to a far narrower area.

6. When routing traces next to a via or between an array of vias, make sure that the via clearance section does

not interrupt the path of the return current on the ground plane below.

7. Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better

impedance matching. Otherwise they will cause the differential impedance to drop below 75

Ω and fail the

board during TDR testing.

8. Use the smallest size possible for signal trace vias and DisplayPort connector pads as they have less impact

on the 100

Ω differential impedance. Large vias and pads can cause the impedance to drop below 85 Ω.

9. Use solid power and ground planes for 100

Ω impedance control and minimum power noise.

10. For 100

Ω differential impedance, use the smallest trace spacing possible, which is usually specified by the

PCB vendor.

11. Keep the trace length between the DisplayPort connector and the DisplayPort device as short as possible to

minimize attenuation.

12. Use good DisplayPort connectors whose impedances meet the specifications.

13. Place bulk capacitors (for example, 10

μF) close to power sources, such as voltage regulators or where the

power is supplied to the PCB.

14. Place smaller 0.1

μF or 0.01 μF capacitors at the device.

11.2 Layout Example

Figure 10. Skew Seduction via Meandering Using Chamfered Corners

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