SPC560D40L1 datasheet(32/90 Pages) STMICROELECTRONICS

32 / 90 page

Electrical characteristics

SPC560D30x, SPC56040Dx

32/90

Doc ID 16315 Rev 7

Note:

SRAM data retention is guaranteed with VDD_LV not below 1.08 V.

VSS_LV

(3)

SR —

Voltage on VSS_LV (low voltage digital supply) pins

with respect to ground (VSS)

—VSS  0.1 VSS +0.1

VDD_BV

(4) SR —

Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)

—4.5

5.5

Voltage drop(2)

3.0

5.5

Relative to VDD VDD  0.1 VDD +0.1

VSS_ADC SR —

Voltage on VSS_HV_ADC (ADC reference) pin with

respect to ground (VSS

—VSS  0.1 VSS +0.1

VDD_ADC

(5)

SR —

Voltage on VDD_HV_ADC pin (ADC reference) with

respect to ground (VSS)

—4.5

5.5

Voltage drop(2)

3.0

5.5

Relative to VDD VDD  0.1 VDD +0.1

VIN

SR —

Voltage on any GPIO pin with respect to ground

(VSS)

—VSS  0.1

—

Relative to VDD

—VDD +0.1

IINJPAD

SR —

Injected input current on any pin during overload

condition

—

55

IINJSUM

SR —

Absolute sum of all injected input currents during

overload condition

—

50

TVDD

SR — VDD slope to ensure correct power up

(6)

—3.0(7)

250 x 103

(0.25

[V/µs])

V/s

100 nF capacitance needs to be provided between each VDD/VSS pair.

Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain analog

electrical characteristics will not be guaranteed to stay within the stated limits.

330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.

470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed

depending on external regulator characteristics).

100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.

Guaranteed by device validation

Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH)

Table 13.

Recommended operating conditions (5.0 V) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

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