RHFLVDS2281 datasheet(9/17 Pages) STMICROELECTRONICS

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RHFLVDS2281

Electrical characteristics

DVOS

Change of magnitude of VOS for

complementary output states

IOS

Output short-circuit current

VID = -400 mV and VOUT- = 0 V

VID = +400 mV and VOUT+ = 0 V

-9

IOZ

High impedance output current

Disabled, VOUT = 3.6 V or 0V

-10

µA

IOFFOUT

LVDS outputs power-off leakage

current

VCC = 0 V, VOUT = 3.6 V

-50

+50

Input to SL setup time(3)

Refer to Figure 5

1.6

Input to SL Hold time(3)

1.5

TSw

SL to Switched output(3)

tPHLD

Propagation delay time, high to

low

VID = 200 mVp-p, input pulse from

1.1 V to 1.3 V, VCM=1.2 V

Load: refer to Figure 3

1.5

tPLHD

Propagation delay time, low to

high

1.5

tSK1

Channel to channel skew(3)(4)

VID = 200 mVp-p

Load: refer to Figure 6

0.6

tSK2

Chip to chip skew(3)(5)

0.7

tSKD

Differential skew(6)



(tPHLD-tPLHD)

0.6

t r

Output signal rise time

Refer to Figure 4

0.9

t f

Output signal fall time

0.9

tPLZ

Propagation delay time, low

level to high impedance output

Refer to Figure 6

2.8

tPHZ

Propagation delay time, high

level to high impedance output

2.8

tPZH

Propagation delay time, high

impedance to high level output

2.5

tPZL

Propagation delay time, high

impedance to low level output

2.5

Fail-safe and cold-spare

tD1

Fail-safe to active time

µs

tD2

Active to fail-safe time

1. Guaranteed by characterization on bench.

2. All pins are floating except pin under test and VCC.

3. Guaranteed by design.

4. tSK1 is the maximum delay time difference between drivers on the same device (with all inputs connected together).

5. tSK2 is the maximum delay time difference between outputs of all devices when they operate with the same supply voltage,

at the same temperature.

6. tSKD is the maximum delay time difference between tPHLD and tPLHD (see Figure 4).

Table 7. Electrical characteristics table (continued)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

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