R6986 datasheet(46/62 Pages) STMICROELECTRONICS

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Application notes

R6986

46/62

DocID026996 Rev 2

Multiple R6986 can be synchronized to an external frequency signal fed to the SYNCH pin.

In this case the set is phased to the reference and all the devices will work with 0° phase

shift.

The frequency range of the synchronization signal is 275 kHz - 2 MHz and the minimum

pulse width is 100 nsec (see Figure 34).

Figure 34. Synchronization pulse definition

Since the slope compensation contribution, that is required to prevent subharmonic

oscillations in peak current mode architecture, depends on the switching frequency, it is

important to select the same switching frequency for all regulators (all of them operate as

SLAVE) one step lower than the reference signal (please refer to Table 6: fSW selection on

page 11). As a consequence, all the regulators have the same resistor connected to the

FSW pin , so the slope compensation is optimized accordingly with the frequency of the

synchronization signal. The slope compensation contribution is latched at power-up and so

fixed during the device operation.

The R6986 normally operates in MASTER mode, driving the SYNCH line at the selected

oscillator frequency as shown in Figure 35 and Figure 36.

In SLAVE mode the R6986 sets the internal oscillator at 250 kHz typ. (see Table 6 on

page 11 - first row) and drives the line accordingly.

Figure 35. R6986 synchronization driving capability

In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the

normal operation, the external master must drive the SYNCH pin with a clock signal

fSYNCHRO

100nsec min.

275kHz < fSYNCHRO < 2MHz

fSYNCHRO

100nsec min.

VCC INT

5 mA

0.7 mA

fOSC

150nsec typ.

HIGH LEVEL

LOW LEVEL

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