R5975D datasheet(14/47 Pages) STMICROELECTRONICS

14 / 47 page

Functional description

R5975D

14/47

DocID026878 Rev 1

Figure 5. Synchronization example

5.4

Current protection

The R5975D features two types of current limit protection; pulse-by-pulse and frequency

foldback.

The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in

Figure 6. The output power PDMOS transistor is split into two parallel PDMOS transistors.

The smallest one includes a resistor in series, RSENSE. The current is sensed through

RSENSE and, if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is

switched off until the next falling edge of the internal clock pulse. Due to this reduction of the

ON time, the output voltage decreases. As the minimum switch-on time necessary to sense

the current, in order to avoid a false overcurrent signal, is too short to obtain a sufficiently

low duty cycle at 250 kHz (see Section 8.5 on page 32), the output current in strong

overcurrent or short-circuit conditions may not be properly limited. For this reason, the

switching frequency is also reduced, therefore keeping the inductor current under its

maximum threshold. The frequency shifter (Figure 4) functions based on the feedback

voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching

frequency decreases also.

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