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LNBH25S bảng dữ liệu(PDF) 13 Page - STMicroelectronics |
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LNBH25S bảng dữ liệu(HTML) 13 Page - STMicroelectronics |
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13 / 37 page ![]() LNBH25S Pin configuration DocID026736 Rev 2 13/37 3 Pin configuration Figure 5: Pin connection (top view) Table 2: Pin description Pin Symbol Name Pin function 2 FLT FLT Open drain output for IC fault conditions. It is set low in case of overload (OLF bit) or overheating status (OTF bit) or power not good (PNG) is detected. To be connected to pull-up resistor (5 V max.) 3 LX NMOS drain Integrated N-channel power MOSFET drain 4 PGND Power ground DC-DC converter power ground. To be connected directly to exposed pad 6 ADDR Address setting Two I²C bus addresses available by setting the address pin level voltage. See Table 16: "Address pin characteristics" 7 SCL Serial clock Clock from I²C bus 8 SDA Serial data Bi-directional data from/to I²C bus 9 ISEL Current selection The resistor “RSEL” connected between ISEL and GND defines the linear regulator current limit threshold. Refer to Section 2.6: "Output current limit selection" and ISET bit description in Table 9: "Data 3 (read/write register. Register address = 0X4)" 15 GND Analog ground Analog circuit ground. To be connected directly to the exposed pad 16 VBYP Bypass capacitor Needed for internal pre-regulator filtering. The VBYP pin connects an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device DSQOUT DSQIN/ EXTM VUP DETIN NC VOUT ADDR 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 12 11 10 19 20 21 22 23 24 GND NC VCC PGND FLT NC LX SDA ISEL NC NC NC NC VBYP BPSW NC SCL 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 12 11 10 19 20 21 22 23 24 GIPG0907141409LM |
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