USB3300 datasheet(17/53 Pages) MICROCHIP

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 2014-2015 Microchip Technology Inc.

DS00001783B-page 17

USB3300

RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3300 uses a low latency

high speed receiver path to lower the RxEndDelay to 43 high speed clocks. This low latency design gives the Link more

cycles to make decisions and reduces the Link complexity. This is the result of the “wrapper less” architecture of the

USB3300. This low RxEndDelay should allow legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to

a ULPI interface.

In Figure 6-2, "ULPI Digital Block Diagram", a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when

the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The

USB3300 is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the transmitter or the ULPI reg-

ister array.

FIGURE 6-2:

ULPI DIGITAL BLOCK DIAGRAM

Data[7:0]

Interrupt

Control

High Speed TX

Full Speed TX

Low Speed TX

High Speed Data

Recovery

Full / Low Speed

Data Recovery

ULPI Protocol

Block

6pinSerial Mode

XcvrSelect[1:0]

TermSelect

OpMode[1:0]

Reset

SuspendM

3pinSerial Mode

ClockSuspendM

AutoResume

Indicator Complement

Indicator Pass Thru

Interface Protect Disable

IdPullUp

DpPulldown

DmPulldown

DischrgVbus

ChrgVbus

DrvVbus

DrvVbusExternal

UseExternal Vbus Indicator

InterruptEnable Rise[4:0]

InterruptEnableFall[4:0]

InterruptStatus[4:0]

InterruptLatch[4:0]

Linestates[1:0]

VbusValid

SessionValid

SessionEnd

HS Tx Data

FS/LS Tx Data

HS RX Data

FS/LS Data

NOTE:

The USB3300 uses

a wrapperless ULPI

interface.

DIR

NXT

STP

Tx Data

Rx Data

POR

ULPI Register

Array

HostDisconnect

IdGnd

To OTG

Module

Transceiver

Control

Module

To USB

Transceiver

From OTG

Module

To USB

Transceiver

RXD CMD

From USB

Transceiver

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