LAN8810 datasheet(9/83 Pages) MICROCHIP

9 / 83 page

 2009-2015 Microchip Technology Inc.

DS00001870B-page 9

LAN8810/LAN8810I

TABLE 2-4:

ETHERNET PINS

Num Pins

Name

Symbol

Buffer

Type

Description

Ethernet TX/

RX Positive

Channel 0

TR0P

AIO

Transmit/Receive Positive Channel 0.

Ethernet TX/

RX Negative

Channel 0

TR0N

AIO

Transmit/Receive Negative Channel 0.

Ethernet TX/

RX Positive

Channel 1

TR1P

AIO

Transmit/Receive Positive Channel 1.

Ethernet TX/

RX Negative

Channel 1

TR1N

AIO

Transmit/Receive Negative Channel 1.

Ethernet TX/

RX Positive

Channel 2

TR2P

AIO

Transmit/Receive Positive Channel 2.

Ethernet TX/

RX Negative

Channel 2

TR2N

AIO

Transmit/Receive Negative Channel 2.

Ethernet TX/

RX Positive

Channel 3

TR3P

AIO

Transmit/Receive Positive Channel 3.

Ethernet TX/

RX Negative

Channel 3

TR3N

AIO

Transmit/Receive Negative Channel 3.

External PHY

Bias Resistor

ETHRBIAS

Used for the internal bias circuits. Connect to an

external 8.06K 1.0% resistor to ground.

TABLE 2-5:

JTAG PINS

Num Pins

Name

Symbol

Buffer

Type

Description

JTAG Test

Data Out

TDO

VO8

JTAG (IEEE 1149.1) data output.

JTAG Test

Data Input

TDI

VIS

(PU)

JTAG (IEEE 1149.1) data input.

Note:

When not used, tie this pin to

VDDVARIO.

JTAG Test

Clock

TCK

VIS

(PD)

JTAG (IEEE 1149.1) test clock.

Note:

When not used, tie this pin to VSS.

JTAG Test

Mode Select

TMS

VIS

(PU)

JTAG (IEEE 1149.1) test mode select.

Note:

When not used, tie this pin to

VDDVARIO.

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