DLPC3433 datasheet(8/62 Pages) TI1

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DLPC3433, DLPC3438

DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016

www.ti.com

Pin Functions – Parallel Port Input Data and Control(1)(2)

DESCRIPTION

I/O

NAME

NUMBER

PARALLEL RGB MODE

BT656 INTERFACE MODE

PCLK

I11

Pixel clock(3)

PDM_CVS_TE

Parallel data mask(4)

Unused(5)

VSYNC_WE

I11

Vsync(6)

Unused(5)

HSYNC_CS

I11

Hsync(6)

Unused(5)

DATAEN_CMD

I11

Data Valid(6)

Unused(5)

(TYPICAL RGB 888)

PDATA_0

Blue (bit weight 1)

BT656_Data (0)

PDATA_1

Blue (bit weight 2)

BT656_Data (1)

PDATA_2

Blue (bit weight 4)

BT656_Data (2)

PDATA_3

Blue (bit weight 8)

BT656_Data (3)

I11

PDATA_4

Blue (bit weight 16)

BT656_Data (4)

PDATA_5

Blue (bit weight 32)

BT656_Data (5)

PDATA_6

Blue (bit weight 64)

BT656_Data (6)

PDATA_7

Blue (bit weight 128)

BT656_Data (7)

(TYPICAL RGB 888)

PDATA_8

Green (bit weight 1)

PDATA_9

Green (bit weight 2)

PDATA_10

Green (bit weight 4)

PDATA_11

Green (bit weight 8)

I11

Unused

PDATA_12

Green (bit weight 16)

PDATA_13

Green (bit weight 32)

PDATA_14

Green (bit weight 64)

PDATA_15

Green (bit weight 128)

(TYPICAL RGB 888)

PDATA_16

Red (bit weight 1)

PDATA_17

Red (bit weight 2)

PDATA_18

Red (bit weight 4)

PDATA_19

Red (bit weight 8)

I11

Unused

PDATA_20

Red (bit weight 16)

PDATA_21

Red (bit weight 32)

PDATA_22

Red (bit weight 64)

PDATA_23

P10

Red (bit weight 128)

3D reference

•

For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the

host when a 3D command is not provided. Must transition in the middle of each frame

3DR

(no closer than 1 ms to the active edge of VSYNC)

•

If a 3D application is not used, then this input should be pulled low through an external

resistor.

(1)

PDATA(23:0) bus mapping is pixel format and source mode dependent. See later sections for details.

(2)

PDM_CVS_TE is optional for parallel interface operation. If unused, inputs should be grounded or pulled down to ground through an

external resistor (8 k

Ω or less).

(3)

Pixel clock capture edge is software programmable.

(4)

The parallel data mask signal input is optional for parallel interface operations. If unused, inputs should be grounded or pulled down to

ground through an external resistor (8 k

Ω or less).

(5)

Unused inputs should be grounded or pulled down to ground through an external resistor (8 k

Ω or less).

(6)

VSYNC, HSYNC, and DATAEN polarity is software programmable.

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