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4.6
Normal SPI Protocols
When operating in normal mode, the SPI bus internal address pointer is incremented depending upon which command has been transmitted. Multiple commands may
be transmitted sequentually so long as the SPI_CS# pin is asserted low. Figure 4-3 shows an example of this operation.
4.6.1
RESET INTERFACE
Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data, the receipt of the
successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation.
FIGURE 4-3:
Example SPI Bus Communication - Normal Mode
SPI_CS#
SPI_MISO
SPI_MOSI
SPI Address Pointer
SPI Data output buffer
Register Address /
Data
7Ah
XXh
(invalid)
XXh
(invalid)
YYh
(invalid)
7Ah
7Dh
41h
YYh
(invalid)
7Eh
66h
XXh
(invalid)
45h
7Dh
41h
AAh
(invalid)
AAh
(invalid)
7Fh
7Fh
55h
(invalid)
66h
7Fh
AAh
7Dh
43h
40h
78h
7Fh
XXh
(invalid)
7Fh
56h
40h / 56h
41h / 45h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h / 78h
41h
45h
40h / 56h
41h / 45h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h / 78h
42h
AAh
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h / 78h
41h
55h
7Fh
AAh
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h / 78h
41h
66h
42h
AAh
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h / 78h
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h / 78h
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h /78h
44h
80h
40h
80h
40h
56h
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h /78h
43h
55h
7Fh
7Fh
55h
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h /78h
80h
45h
43h
46h
78h
40h / 56h
41h / 66h
42h / AAh
43h / 55h
44h / 80h
45h / 43h
46h / 78h
00h
XXh
Indicates SPI Address pointer incremented



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