EM346-RTR datasheet(76/142 Pages) SILABS

tên linh kiện	EM346-RTR

Giải thích chi tiết về linh kiện	High-Performance, Integrated Dual ZigBee PRO

PDF	142 Pages

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nhà sản xuất	SILABS [Silicon Laboratories]

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76 / 142 page

EM346

Rev 1.0

8.3.5. Interrupts

SPI slave controller second-level interrupts are generated on the following events:



Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE, either the 0 to 1

transition or the high level of SC_SPITXIDLE)



Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0 to 1 transition or the

high level of SC_SPITXFREE)



Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either the 0 to 1 transition

or the high level of SC_SPIRXVAL)



Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)



Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)



Received and lost character while receive FIFO was full (receive overrun error)



Transmitted character while transmit FIFO was empty (transmit underrun error)

To enable CPU interrupts, set desired interrupt bits in the second-level INT_SCxCFG register, and also enable the

top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.

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