TAS5760LDAPR datasheet(5/77 Pages) TI1

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TAS5760L

www.ti.com

SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015

Pin Functions (continued)

TAS5760L

NO.

TYPE(1)

INTERNAL TERMINATION

DESCRIPTION

NAME

Connection point for the SPK_OUTA- bootstrap capacitor, which is used to

BSTRPA-

create a power supply for the high-side gate drive for SPK_OUTA-

Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to

BSTRPA+

create a power supply for the high-side gate drive for SPK_OUTA

Connection point for the SPK_OUTB- bootstrap capacitor, which is used to

BSTRPB-

create a power supply for the high-side gate drive for SPK_OUTB-

Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to

BSTRPB+

create a power supply for the high-side gate drive for SPK_OUTB+

Ground for digital circuitry (NOTE: This pin should be connected to the

DGND

system ground)

DVDD

Power supply for the internal digital circuitry

Dual function pin that functions as an I²C data input pin in I²C Control Mode

FREQ/SDA

Weak Pull-Down

or as a Frequency Select terminal when in Hardware Control Mode.

Ground for gate drive circuitry (this terminal should be connected to the

GGND

system ground)

Voltage regulator derived from PVDD supply (NOTE: This pin is provided as

GVDD_REG

a connection point for filtering capacitors for this supply and must not be

used to power any external circuitry)

Word select clock for the digital signal that is active on the serial port's input

LRCK

Weak Pull-Down

data line

Master Clock used for internal clock tree, sub-circuit/state machine, and

MCLK

Weak Pull-Down

Serial Audio Port clocking

Not connected inside the device (all "no connect" pins should be connected

18-

to ground for best thermal performance, however they can be used as

routing channels if required.)

Dual function pin that functions as an I²C clock input terminal in I²C Control

PBTL/SCL

Weak Pull-Down

Mode or configures the device to operate in pre-filter Parallel Bridge Tied

Load (PBTL) mode when in Hardware Control Mode

36,

Ground for power device circuitry (NOTE: This terminal should be

PGND

connected to the system ground)

32,

33,

PVDD

Power Supply for internal power circuitry

44,

Bit clock for the digital signal that is active on the serial data port's input

SCLK

Weak Pull-Down

data line

SDIN

Weak Pull-Down

Data line to the serial data port

SFT_CLIP

sets the maximum output voltage before clipping

Speaker amplifier fault terminal, which is pulled LOW when an internal fault

SPK_FAULT

occurs

SPK_GAIN0

Weak Pull-Down

Adjusts the LSB of the multi-bit gain of the speaker amplifier

SPK_GAIN1

Weak Pull-Down

Adjusts the MSB of the multi-bit gain of the speaker amplifier

SPK_SLEEP/

In Hardware Control Mode, places the speaker amplifier in sleep mode. In

Weak Pull-Up

ADR

Software Control Mode, is used to determine the I²C Address of the device

SPK_OUTA-

Negative pin for differential speaker amplifier output A

SPK_OUTA+

Positive pin for differential speaker amplifier output A

SPK_OUTB-

Negative pin for differential speaker amplifier output B

SPK_OUTB+

Positive pin for differential speaker amplifier output B

SPK_SD

Places the speaker amplifier in shutdown

VCOM

Bias voltage for internal PWM conversion block

Provides both electrical and thermal connection from the device to the

board. A matching ground pad must be provided on the PCB and the

PowerPAD™

device connected to it via solder. For proper electrical operation, this

ground pad must be connected to the system ground.

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