AS3695C datasheet(15/40 Pages) AMSCO

15 / 40 page

AS3695C

austriamicrosystems

www.austriamicrosystems.com

Rev 1.11 / 2010-12-08

14 - 39

4.2.7 PLL

The PLL frequency synthesizer can be used to generate PWM-clock frequencies fclk between 125kHz

and 2MHz derived from input frequencies between 60HZ and 480Hz.

The VCO frequency can be calculated:

The output frequency can be calculated:

where:

Range

fin

Input frequency

60 Hz – 480Hz

fclk

Output frequency

125kHz – 2MHz

fVCO

VCO frequency

1MHz – 2MHz

NCdiv

counter

35 - 2051

ACdiv

counter

0 - 31

ODdiv

Output divider

1,2,3,4,6,8

The main blocks of the PLL are the Phase-Frequency-Detector, the Loop Filter, the VCO and the

divider.

4.2.7.1

Phase-Frequency-Detector (PFD)

The block diagram of the phase-frequency-comparator is shown below. The output signal on pin “Filt1”

is a switched current source ( ICP ) which is sinking or sourcing current depending of the frequency and

phase difference of fin and fVCO/M.

fin

Filt1

Filt2

VCO

NCdiv

fvco

35-2051

Loop Filter

ODdiv

fclk

PFD

1,2,3,4,6,8

1MHz - 2MHz

ACdiv

0-31

fin

fvco/M

Filt1

SW1

SW2

ICP

fin

fvco/N

SW1

Filt1

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