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AS3693B bảng dữ liệu(PDF) 7 Page - ams AG |
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AS3693B bảng dữ liệu(HTML) 7 Page - ams AG |
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7 / 33 page ![]() AS3693B austriami crosyst ems www.austriamicrosystems.com Revision 1.21 / 2011-09-30 6 - 32 5.3 Electrical Characteristics Table 3 – Analog Electrical Characteristics Symbol Parameter Min Typ Max Unit Note VCURR Voltage at CURR1 to CURR16 50.0 V ICURR, TOL Current Source Tolerance -0.5 +0.5 % Using 250mV reference @25C TJUNCTION, excluding variation of external resistors -1.5 +1.5 % Using 250mV reference -20°C to +100°C (1) T JUNCTION, -20°C to +85°C TAMB, excluding variation of external resistors; V(CURRx) <= 4.0V -1.6 +1.6 % Using DAC reference VDAC =250mV ( Data = 0x80 ) @25C TJUNCTION, excluding variation of external resistors DAC_INL DAC INL -4 +4 LSB DAC integral nonlinearity VC Automatic Supply Regulation trip point 0.5 1 V See section ‘Feedback Circuit (DCDC_Regulation_Trip_Point)’. VC,GAIN Automatic Supply Regulation gain 2.0 mA/V Voltage to current ratio; output current range typ. 0 to 200uA TOVTEMP Over temperature Limit 130 140 150 °C Maximum junction temperature (2) Thyst Over temperature hysteresis 10 °C CLK Internal Clock for PWM 400 500 600 KHz Clock for internal PWM generation Notes: 1, Accuracy at +100°C guaranteed by design and verified by laboratory characterization 2, If the temperature exceeds the over temperature limit, the PWM will be turned off. If the temperature decreases, the PWM is activated again. The register settings are not reset. Table 4 – Digital Input pins characteristics (SDI,VSYNC,HSYNC,SCL,CS) Symbol Parameter Min Typ Max Unit Note VIH High Level Input voltage 1.3 VREG V VIL Low Level Input voltage -0.3 0.4 V f_SCL Maximum SCL Frequency 10 MHz f_HSYNC Maximum HSYNC Frequency 10 MHz Output driver is slew rate limited ( Register: Curreg_Control 0x0D ) ts_VH Vsync setup time before rising edge of Hsync 15 ns SYNC-mode: PWM values are updated with first rising edge of Hsync while Vsync = 1 ( see 7.3.1.1 ) th_VH Vsync hold time after rising edge of Hsync 15 ns ts_SCISCL Setup time SDI,SCL 15 ns SPI interface mode th_SCLSCI Hold time SCL,SDI 15 ns SPI interface mode ts_CSSCL Setup time CS,SCL 15 ns SPI interface mode |
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