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AS3435 bảng dữ liệu(PDF) 59 Page - ams AG |
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AS3435 bảng dữ liệu(HTML) 59 Page - ams AG |
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59 / 102 page ![]() ams Datasheet, Confidential: 2014-Jun-13 [v1-30] AS3415/AS3435 – 59 Detaile d Desc rip t ion The I²C addresses for the devices in the different connection modes can be found in Figure 74. Figure 74: I²C Slave Address Table I²C Slave Address Table: Shows the two I²C addresses for the AS3515/35 depending on the master connection. When the I²C master is accessing two devices on the bus it is important not violating the minimum bus idle time of 2.5ms. Thus, if the I²C master is communicating with device one it is not possible to read/write for example from device two right after a read/write command has been sent to device one without a minimum bus idle time of 2.5ms. Due to the reason that the AS3415/35 does not have a dedicated I²C address selection pin this idle time is necessary to recover the internal I²C address selection block for a correct I²C slave address detection. The I²C address selection timing diagram in Figure 75 shows the necessary bus idle time. Figure 75: I²C Address Selection Timing DEVICE Number 7 bit I²C address 8 Bit read address 8 Bit write address 1(default) 0x47 0x8F 0x8E 2 0x46 0x8D 0x8C I2C Bus Traffic DEVICE1:WRITE DEVICE1:READ DEVICE1:WRITE DEVICE1:READ BUS IDLE I2C Bus Traffic DEVICE2:WRITE DEVICE2:READ DEVICE2:WRITE DEVICE2:READ BUS Condition Target Device >2.5ms |
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