Connection Diagrams

Logic Diagram

Functional Description

The ’AC/’ACT169 uses edge-triggered J-K-type flip-flops

and have no constraints on changing the control or data in-

put signals in either state of the Clock. The only requirement

is that the various inputs attain the desired state at least a

setup time before the rising edge of the clock and remain

valid for the recommended hold time thereafter. The parallel

load operation takes precedence over the other operations,

as indicated in the Mode Select Table. When PE is LOW, the

data on the P

ing edge of the Clock. In order for counting to occur, both

CEP and CET must be LOW and PE must be HIGH; the U/D

input then determines the direction of counting. The Terminal

Count (TC) output is normally HIGH and goes LOW, pro-

vided that CET is LOW, when a counter reaches zero in the

Count Down mode or reaches 15 in the Count Up mode. The

TC output state is not a function of the Count Enable Parallel

(CEP) input level. If an illegal state occurs, the ’AC169 will

return to the legitimate sequence within two counts. Since

Pin Assignment

for DIP and Flatpak

DS100276-3

Pin Assignment

for LCC

DS100276-4

DS100276-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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