PCA9564D datasheet(22/31 Pages) PHILIPS

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Philips Semiconductors

Product data

PCA9564

Parallel bus to I2C-bus controller

2003 Apr 02

SDA

SCL

SU01755

tHD;STA

tLOW

tHD;DAT

tSU;DAT

tHIGH

tSU;STA

tHD;STA

tSP

tSU;STO

tBUF

Figure 18. Definition of timing

I2C-BUS TIMING SPECIFICATIONS

All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 2.5 V ± 0.2 V and 3.3 V ± 0.3 V,

Tamb = -40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.

SYMBOL

PARAMETER

STANDARD MODE

I2C BUS

FAST MODE

I2C BUS

UNITS

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

UNITS

fSCL

Operating frequency

100

400

kHz

tBUF

Bus free time between STOP and START conditions

4.7

—

1.3

—

µs

tHD;STA

Hold time after (repeated) START condition

4.0

—

0.6

—

µs

tSU;STA

Repeated START condition setup time

4.7

—

0.6

—

µs

tSU;STO

Setup time for STOP condition

4.0

—

0.6

—

µs

tHD;DAT

Data in hold time

—

tVD;ACK

Valid time for ACK condition

—

0.6

—

0.6

µs

tVD;DAT(L)

Data out valid time LOW

—

0.6

—

0.6

µs

tVD;DAT(H)

Data out valid time HIGH

—

0.6

—

0.6

µs

tSU;DAT

Data setup time

250

—

100

—

tLOW

Clock LOW period

4.7

—

1.3

—

µs

tHIGH

Clock HIGH period

4.0

—

0.6

—

µs

Clock/Data fall time

—

0.3

—

0.3

µs

Clock/Data rise time

—

0.3

µs

tSP

Pulse width of spikes that must be suppressed by the input filters

—

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