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AS4LC8M8S0 bảng dữ liệu(PDF) 17 Page - Alliance Semiconductor Corporation |
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AS4LC8M8S0 bảng dữ liệu(HTML) 17 Page - Alliance Semiconductor Corporation |
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17 / 24 page ![]() ® AS4LC8M8S0 AS4LC4M16S0 7/5/00 ALLIANCE SEMICONDUCTOR 17 write cycle Precharge command A Precharge command can be used to interrupt burst read/write operation during the read cycle. During RD, burst read is terminated and o/p goes to High Z after CAS latency. The same bank can be activated after tRP. During write, burst write operation is terminated immediately. Data written two cycles prior to the precharge command will be correctly stored. Set DQM high one cycle before Precharge command and hold it high until Precharge command to mask and avoid writing invalid data. read cycle (CL = 2) read cycle (CL = 3) write cycle (BL = 8) CLK CMD DQ Burst stop Write data (CL = 2,3) Q0 Q1 Q2 Q3 CLK CMD DQ Read data PRE ACT Q0 Q1 Q2 Q3 tRP CLK CMD DQ Read data PRE ACT Q0 Q1 Q2 Q3 CLK CMD DQ Write data PRE ACT D0 D1 D2 Q4 tRP D3 Masked DQM |
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