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Z86E73 bảng dữ liệu(PDF) 13 Page - Zilog, Inc. |
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Z86E73 bảng dữ liệu(HTML) 13 Page - Zilog, Inc. |
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13 / 19 page ![]() 13 PRELIMINARY Z86E73/E74/L73/L74 CP95LVO0801 AC CHARACTERISTICS (Z86L73/L74) External I/O or Memory Read and Write Timing Table T A = 0°C to +70°C V CC 8.0 MHz No. Symbol Parameter Note [3] Min Max Units Notes 1 TdA(AS) Address Valid to 2.0V 55 ns [2] /AS Rising Delay 3.9V 55 ns 2 TdAS(A) /AS Rising to Address 2.0V 70 ns [2] Float Delay 3.9V 70 ns 3 TdAS(DR) /AS Rising to Read 2.0V 400 ns [1, 2] Data Required Valid 3.9V 400 ns 4 TwAS /AS Low Width 2.0V 80 ns [2] 3.9V 80 ns 5 Td Address Float to 2.0V 0 ns /DS Falling 3.9V 0 ns 6 TwDSR /DS (Read) Low Width 2.0V 300 ns [1, 2] 3.9V 300 ns 7 TwDSW /DS (Write) Low Width 2.0V 165 ns [1, 2] 3.9V 165 ns 8 TdDSR(DR) /DS Falling to Read 2.0V 260 ns [1, 2] Data Required Valid 3.9V 260 ns 9 ThDR(DS) Read Data to 2.0V 0 ns [2] /DS Rising Hold Time 3.9V 0 ns 10 TdDS(A) /DS Rising to Address 2.0V 85 ns [2] Active Delay 3.9V 95 ns 11 TdDS(AS) /DS Rising to /AS 2.0V 60 ns [2] Falling Delay 3.9V 70 ns 12 TdR/W(AS) R//W Valid to /AS 2.0V 70 ns [2] Rising Delay 3.9V 70 ns 13 TdDS(R/W) /DS Rising to 2.0V 70 ns [2] R//W Not Valid 3.9V 70 ns 14 TdDW(DSW) Write Data Valid to /DS 2.0V 80 ns [2] Falling (Write) Delay 3.9V 80 ns 15 TdDS(DW) /DS Rising to Write 2.0V 70 ns [2] Data Not Valid Delay 3.9V 80 ns 16 TdA(DR) Address Valid to Read 2.0V 475 ns [1, 2] Data Required Valid 3.9V 475 ns 17 TdAS(DS) /AS Rising to 2.0V 100 ns [2] /DS Falling Delay 3.9V 100 ns 18 TdDM(AS) /DM Valid to /AS 2.0V 55 ns [2] Falling Delay 3.9V 55 ns 19 TdDS(DM) /DS Rise to 2.0V 70 ns /DM Valid Delay 3.9V 70 ns 20 ThDS(A) /DS Rise to Address 2.0V 70 ns Valid Hold Time 3.9V 70 ns Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] 2.0V to 3.9V. Standard Test Load. All timing references use 0.9 V CC for a logic 1 and 0.1 VCC for a logic 0. |
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