Z87L01 datasheet(33/51 Pages) ZILOG

33 / 51 page

Z87001/Z87L01

Zilog

ROMless Spread Spectrum Cordless Phone Controller

DS96WRL0800

P R E L I M I N A R Y

The Z87001 DSP core processor has four banks of eight

registers mapped in the core processor’s “external regis-

ter” space, as summarized in the following table.

Table 10. Register Summary

BANK ADDRESS

READ DESCRIPTION

WRITE DESCRIPTION

TABLE #

Bank 3

EXT0

CONFIG1

Clock Dividers, Use Core Bias,

SYLE polarity, search window

size, Bias Threshold

Table 25

EXT1

CONFIG2

Remaining Sleep time

ANT0/1 control, Sleep Period Table 26

EXT2

SSPSTATE

Stop VP clock, Absent gain, Bias Enable, Tx Enable, Sync

Search control, Hop Enable, Frame Start control, Multiplex

control, Sleep mode control

Table 27

EXT3

SSPSTATUS

Frame Counter, Handset/Base,

Sync Search control, Frame

Start control

Table 28

EXT4

GPIO0DIR

General-Purpose I/O port 0 direction control

Table 29

EXT5

GPIO0DATA

General-Purpose I/O port 0 data

Table 30

EXT6

GPIO1DIR

General-Purpose I/O port 1 direction control

Table 31

EXT7

GPIO1DATA

General-Purpose I/O port 1 data

Table 32

Bank 2

EXT0

VP_INOUT

ADPCM Processor Status

ADPCM Processor Command Table 33

EXT1

RX_CONTROL

SNR estimate

UW location

Table 34

EXT2

BIAS_ERROR

FCW value

Table 35

EXT3

RSSI

8-bit ADC data (RSSI)

Table 36

EXT4

CORE_BIAS

Core Bias data

Table 37

EXT5

MOD_PWR_CTRL

MOD_PWR control

Table 38

EXT6

DEMOD_PWR_CTRL

RXSW, RFEON pin control

Table 39

EXT7

RFTX_PWR_CTRL

PAON pin control

Table 40

Bank 1

EXT0

RATE_BUF_ADDR

Rate Buffer address

Table 41

EXT1

RATE_BUF_DATA

Re Rate Buffer data

Tx Rate Buffer data, control

data

Table 42

EXT2

BIT_SYNC

Bit Sync monitoring

Bit Sync control

Table 43

EXT3

RESERVED

Table 44

EXT4

RESERVED

Table 44

EXT5

RESERVED

Table 44

EXT6

CONTROL

INT, WAKEUP pin control, 4-bit DAC data (PWLV)

Table 45

EXT7

RESERVED

Table 46

Bank 0

EXT0

RESERVED

Table 47

EXT1

RESERVED

Table 47

EXT2

RESERVED

Table 47

EXT3

RESERVED

Table 47

EXT4

RESERVED

Table 47

EXT5

RESERVED

Table 47

EXT6

INT_SYM_ERR0

Bit Sync monitoring

Table 47

EXT7

RFRX_PWR_CTRL

TXSW, RXSW pin control

Table 49

Z87L01 bảng dữ liệu(PDF) 33 Page - Zilog, Inc.

Z87L01 bảng dữ liệu(HTML) 33 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

bảng dữ liệu tải về

Link URL