Z86L79 datasheet(2/58 Pages) ZILOG

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Z86L79/80

Low-Voltage Microcontroller

Zilog

3-2

P R E L I M I N A R Y

DS97LVO0601

GENERAL DESCRIPTION (Continued)

Z8® applications demand powerful I/O capabilities. The

Z86L79/80 fulfills this with two package options with 24

pins of dedicated input and output. These lines are

grouped into three ports. Each port consists of eight lines

and is configurable under software control to provide tim-

ing, status signals, and parallel I/O.

There are three basic address spaces available to support

a wide range of configurations: Program Memory, Register

File, and Expanded Register File. The Register File is

composed of 256 bytes of RAM. It includes four I/O port

registers, ten control and status registers, and the rest are

general purpose registers. The Expanded Register File

consists of three register groups.

To unburden the program from coping with such real-time

problems as generating complex waveforms or receiving

and demodulating complex waveform/pulses, the Z86L7X

family offers a new intelligent counter/timer architecture

with 8-bit and 16-bit counter/timers (Figure 1). Also includ-

ed are a large number of user-selectable modes, and two

on-board comparators to process analog signals with sep-

arate reference voltages (Figure 2).

Notes: All Signals with a preceding front slash, "/", are ac-

tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is

active Low, only).

Power connections follow conventional descriptions be-

low:

Connection

Circuit

Device

Power

VCC

VDD

Ground

GND

VSS

Figure 1. Counter/Timer Block Diagram

HI16

LO16

16-Bit

T16

TC16H

TC16L

HI8

LO8

And/Or

Logic

Clock

Divider

Glitch

Filter

Edge

Detect

Circuit

8-Bit

TC8H

TC8L

Input

SCLK

2 48

Timer 16

Timer 8/16

Timer 8

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