Z86L71 datasheet(48/61 Pages) ZILOG

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Z86L70/71/75/C71

IR/Low-Voltage Microcontroller

Zilog

1-48

P R E L I M I N A R Y

DS97LVO0500

FUNCTIONAL DESCRIPTION (Continued)

WDT Time Select (D0, D1). Selects the WDT time period.

It is configured as shown in Table 6.

WDTMR During HALT (D2). This bit determines whether

or not the WDT is active during HALT Mode. A 1 indicates

active during HALT. The default is 1.

WDTMR During STOP (D3). This bit determines whether

or not the WDT is active during STOP Mode. Since the

XTAL clock is stopped during STOP Mode, the on-board

RC has to be selected as the clock source to the

WDT/POR counter. A 1 indicates active during STOP. The

default is 1.

Clock Source for WDT (D4). This bit determines which

oscillator source is used to clock the internal POR and

WDT counter chain. If the bit is a 1, the internal RC oscil-

lator is bypassed and the POR and WDT clock source is

driven from the external pin, XTAL1. The default configu-

ration of this bit is 0, which selects the RC oscillator.

Table 6. WDT Time Select

Time-Out of

Internal RC OSC

Time-Out of

XTAL Clock

5 ms min

256 TpC

10 ms min

512 TpC

20 ms min

1024 TpC

80 ms min

4096 TpC

Notes:

1. TpC = XTAL clock cycle.

2. The default on reset is 10 ms.

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