Z86C9620VSC datasheet(25/46 Pages) ZILOG

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Z86C61/62/96

Z8® MICROCONTROLLER

To accommodate polled interrupt systems, interrupt in-

puts are masked and the Interrupt Request register is

polled to determine which of the interrupt requests

need service. Software initialed interrupts are supported

by setting the appropriate bit in the Interrupt Request

Internal interrupt requests are sampled on the falling edge

of the last cycle of every instruction. The interrupt request

must be valid 5TpC before the falling edge of the last clock

cycle of the currently executing instruction.

For the ROMless mode, when the device samples a valid

interrupt request, the next 48 (external) clock cycles are

used to prioritize the interrupt, and push the two PC bytes

and the FLAG register onto the stack. The following nine

cycles are used to fetch the interrupt vector from external

memory. The first byte of the interrupt service routine is

fetched beginning on the 58th TpC cycle following the

internal sample point, which corresponds to the 63rd TpC

cycle following the external interrupt sample point.

Interrupts. The Z86C61/62/96 has six different interrupts

from eight different sources. The interrupts are maskable

and prioritized. The eight sources are divided as follows:

four sources are claimed by Port 3 lines P33-P30, one in

Serial Out, one is Serial In, and two in the counter/timers

(Figure 23). The Interrupt Mask Register globally or indi-

vidually enables or disables the six interrupt requests.

When more than one interrupt is pending, priorities are

resolved by a programmable priority encoder that is con-

trolled by the Interrupt Priority register. All Z86C61/62/96

interrupts are vectored through locations in the program

memory. When an interrupt machine cycle is activated, an

interrupt request is granted. Thus, this disables all of the

subsequent interrupts, saves the Program Counter and

Status Flags, and then branches to the program memory

vector location reserved for that interrupt. This memory

location and the next byte contain the 16-bit address of

the interrupt service routine for that particular interrupt

request.

IRQ

IMR

IPR

PRIORITY

LOGIC

Global

Interrupt

Enable

Vector Select

Interrupt

Request

IRQ0 - IRQ5

Figure 23. Interrupt Block Diagram

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