Z86C8316VSC datasheet(39/46 Pages) ZILOG

39 / 46 page

Z86C83/C84

® MCU Microcontrollers

DS96DZ80203

EXPANDED REGISTER FILE CONTROL REGISTERS (0C)

Figure 40. ADC Control Register 0 (Read/Write)

Figure 41. ADC Control Register 1 (Read/Write)

Figure 42. AD Result Register (Read Only)

D7 D6

ADC0 (OC) 8H

Scan 0 = No action.*

1 = Convert channel then stop.

IN/Input/Output Control

0 = No Action (Digital Function)*

1 = Enable Selected Channel

2, M1, M0) as analog input on

associated Port P27-P20

Channel Select (bits 2,1,0)

CSEL2

CSEL1

CSEL0

Channel

* Default setting after reset.

Must be 0 0 1

ADC1 Bank C, Register 9

ADE

0 Disable*

1 Enable

Must be 0.

D5 D4

50 % AGND Offset

35% AGND Offset

Reserved

No Offset

Reserved (Must be 1.)

D7 D6

ADR1 (OC) AH

Data

Figure 43. D/A 1 Control Register

Figure 44. D/A 2 Control Register

Figure 45. D/A 1 Data Register

Figure 46. D/A 2 Data Register

DAC1 Gain

0 0 1 X

0 1 1/2 X

1 0 1 Not Used

1 1 1/4 X

DACR1 Bank C, Register 4

DAC1 Enable

0 Disable

1 Enable

Reserved (Must be 0)

DAC2 Gain

0 0 1 X

0 1 1/2 X

1 0 1 Not Used

1 1 1/4 X

DACR2 Bank C, Register 5

DAC2 Enable

0 Disable

1 Enable

Reserved (Must be 0)

DAC1 Bank C, Register 6

0 = Low Level

1 = High Level

DAC2 Bank C, Register 7

0 = Low Level

1 = High Level

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