Z86C2116FSC datasheet(15/35 Pages) ZILOG

15 / 35 page

Z86C21 MCU

WITH

8K ROM

Counter/Timers. There are two 8-bit programmable

counter/timers (T0-T1), each driven by its own 6-bit pro-

grammable prescaler. The T1 prescaler is driven by inter-

nal or external clock sources; however, the T0 prescaler is

driven by the internal clock only (Figure 15).

The 6-bit prescalers divides the input frequency of the

clock source by any integer number from 1 to 64. Each

prescaler drives its counter, which decrements the value

(1 to 256) that has been loaded into the counter. When both

the counter and prescaler reach the end of the count, a

timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is gener-

ated.

The counter can be programmed to start, stop, restart to

continue, or restart from the initial value. The counters can

also be programmed to stop upon reaching zero (single

pass mode) or to automatically reload the initial value and

continue counting (modulo-n continuous mode).

The counter, but not the prescalers, can be read at any

time without disturbing their value or count mode. The

clock source for T1 is user-definable and can be either the

internal microprocessor clock divided by four, or an exter-

nal signal input through Port 3. The Timer Mode register

configures the external timer input (P31) as an external

clock, a trigger input that is retriggerable or non-

retriggerable, or as a gate input for the internal clock. Port

3, line P36, also serves as a timer output (T

OUT) through

which T0, T1 or the internal clock is output. The counter/

timers are cascaded by connecting the T0 output to the

input of T1.

OSC

PRE0

Initial Value

Current Value

6-Bit

Down

Counter

8-bit

Down

Counter

÷4

6-Bit

Down

Counter

8-Bit

Down

Counter

PRE1

Initial Value

Current Value

÷2

Clock

Logic

IRQ4

IRQ5

Internal Data Bus

Write

Read

Internal Clock

Gated Clock

Triggered Clock

TIN P31

Write

Read

Internal Data Bus

External Clock

Internal

Clock

÷4

Serial I/O

Clock

Tout

P36

÷2

Figure 15. Counter/Timers Block Diagram

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