NCP81040 datasheet(13/28 Pages) ONSEMI

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NCP81040

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The CPU current can also be monitored over the I2C

Interface. The current limit and the load−line can be adjusted

from the circuit component values over the I2C Interface.

Current Limit Set−Point

The current limit threshold on the NCP81040 is

programmed by a resistor between the ILIMFS pin and the

CSCOMP pin. The ILIMFS current, IILIMFS, is compared

with an internal current reference of 20

mA. If IILIMFS

exceeds 20

mA then the output current has exceeded the limit

and the current limit protection is tripped.

ILIMFS +

ILIMFS * VCSCOMP

ILIMFS

(eq. 1)

Where VILIMFS = VCSREF

CSREF * VCSCOMP +

LOAD

(eq. 2)

ILIMFS +

CSREF * VCSCOMP

ILIMFS

Assuming that:

L + 1mW

(eq. 3)

i.e. the external circuit is set up for a 1 m

W load−line then

the RILIMFS is calculated as follows:

ILIMFS +

LOAD

ILIMITFS

(eq. 4)

Assuming we want a current limit of 150 A that means that

ILIMFS must equal 25

mA at that load.

mA +

150 A

ILIMITFS

+ 6kW

(eq. 5)

Solving this equation for RLIMITFS we get 6 k

The current limit threshold can be modified from the

resistor programmed value by using the I2C interface using

Bits <4:0> of the Current Limit Threshold command

(0xE2). The limit is programmable between 50% of the

external limit and 146.7% of the external limit. The

resolution is 3.3%. Table 3 gives some examples codes.

Table 3. Current Limit

Code

Current Limit (% of External Limit)

0 0000

50%

0 0001

53.3%

1 0000

100% = default

1 0001

103.3%

1 1110

143.3%

1 1111

146.7%

Current Limit, Short−Circuit and Latchoff Protection

If the current limit is reached and TD5 has completed, an

internal latchoff delay time will start, and the controller will

shut down if the fault is not removed. This delay is four times

longer than the delay time during the startup sequence. The

current limit delay time only starts after TD5 has completed.

If there is a current limit during startup, the NCP81040 will

go through TD1 to TD5 and then start the latchoff time.

Because the controller continues to cycle the phases during

the latchoff delay time, if the short is removed before the

timer is complete, the controller can return to normal

operation.

The latchoff function can be reset by either removing/

reapplying the supply voltage to the NCP81040, or by

toggling the EN pin low for a short time.

During startup when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground.

This secondary current limit limits the internal COMP

voltage to the PWM comparators to 1.5 V. This limits the

voltage drop across the low−side MOSFETs through the

current balance circuitry. Typical overcurrent latchoff

waveforms are shown in Figure 9.

Figure 9. Overcurrent Latchoff Waveforms

An inherent per phase current limit protects individual

phases if one or more phases stop functioning because of a

faulty component. This limit is based on the maximum

normal mode COMP voltage.

Output Current Monitor

IMON is an analog output from the NCP81040

representing the total current being delivered to the load. It

outputs an accurate current that is directly proportional to

the current set by the ILIMFS resistor.

IMON + 10

ILIMFS

(eq. 6)

The current is then run through a parallel RC connected

from the IMON pin to the FBRTN pin to generate an

accurately scaled and filtered voltage as per the

specification. The size of the resistor is used to set the IMON

scaling.

The scaling is set such that IMON = 900 mV at the TDC

current of the processor. This means that the RIMON resistor

should be chosen as follows.

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