LE25S40AMC

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14. Hardware Data Protection

LE25S40A incorporates a power-on reset function. The following conditions must be met in order to ensure that the

power reset circuit will operate stably.

No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.

Figure 19. Power-down Timing

Power-on timing

Parameter

Symbol

spec

unit

min

max

power-on to operation time

tPU

500

s

power-down time

tPD

10

ms

power-down voltage

VBOT

0.2

V

15. Software Data Protection

The LE25S40A eliminates the possibility of unintentional operations by not recognizing commands under the

following conditions.

 When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)

 When the page program data is not in 1-byte increments

 When the status register write command is input for 2 bus cycles or more

16. Decoupling Capacitor

A 0.1

F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure

that the device will operate stably.

VDD(Max)

VDD(Min)

VDD

0V

vBOT

tPD