GD25Q21 datasheet(36/49 Pages) ELM

36 / 49 page

Rev.1.1

49 -

http://www.elm-tech.com

GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash

7.27. High Performance Mode (HPM) (A3H)

It is recommended to execute High Performance Mode (HPM) command prior to Dual or Quad I/O commands

when operating at high frequencies (see fC in AC Electrical Characteristics). This command allows pre-charging

of internal charge pumps so the voltages required for accessing the flash memory array are readily available.

The command sequence: CS# goes low → Sending A3H command → Sending 3-dummy byte → CS# goes

high. See Figure32. After the HPM command is executed, the device will maintain a slightly higher standby

current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can

be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will also

release the device from HPM mode back to deep power down state.

Figure 32. High Performance Mode Sequence Diagram

Command

0 1 2 3 4 5 6 7

A3H

CS#

SCLK

8 9

29 30 31

MSB

2 1 0

3 Dummy Bytes

23 22

High Performance Mode

HPM

7.28. Erase Security Registers (44H)

The GD25Q21B provides three 512-byte Security Registers which can be erased and programmed individually.

These registers may be used by the system manufacturers to store security and other important information

separately from the main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command

→ CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of the

command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon

as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While

the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write

in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle,

and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch

(WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect

the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase

Security Registers command will be ignored.

Address

A23-16

A15-12

A11-9

A8-0

Security Register #1

00H

0 0 0 1

0 0 0

Do not care

Security Register #2

00H

0 0 1 0

0 0 0

Do not care

Security Register #3

00H

0 0 1 1

0 0 0

Do not care

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