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t, TIME
Figure 11. Reverse Recovery Time (trr)
di/dt = 300 A/
µs
Standard Cell Density
High Cell Density
tb
trr
ta
trr
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves de-
fine the maximum simultaneous drain−to−source vol-
tage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maxi-
mum peak junction temperature and a case temperature
(TC) of 25°C. Peak repetitive pulsed power limits are de-
termined by using the thermal response data in conjunc-
tion with the procedures discussed in AN569, “Transient
Thermal Resistance − General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 µs. In addition
the total power averaged over a complete switching cycle
must not exceed (TJ(MAX) − TC)/(RθJC).
A power MOSFET designated E−FET can be safely
used in switching circuits with unclamped inductive
loads. For reliable operation, the stored energy from cir-
cuit inductance dissipated in the transistor while in ava-
lanche must be less than the rated limit and must be
adjusted for operating conditions differing from those
specified. Although industry practice is to rate in terms
of energy, avalanche energy capability is not a constant.
The energy rating decreases non−linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
10
VGS = 12 V
SINGLE PULSE
TC = 25°C
10
0.1
10 ms
1
100
100
1 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT



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