LM71 datasheet(5/21 Pages) TI

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LM71, LM71-Q1

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SNIS125D – MARCH 2004 – REVISED MARCH 2013

SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS

Unless otherwise noted, these specifications apply for V

+ = 2.65V to 3.6V(1); C

L (load capacitance) on output lines = 100 pF

unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless

otherwise noted.

Units

Symbol

Parameter

Conditions

Typical(2)

Limits(3)

(Limit)

0.16

μs (min)

SC (Clock) Period

(max)

CS Low to SC (Clock) High Set-Up Time

100

ns (min)

CS Low to Data Out (SO) Delay

ns (max)

SC (Clock) Low to Data Out (SO) Delay

ns (max)

CS High to Data Out (SO) TRI-STATE

200

ns (max)

SC (Clock) High to Data In (SI) Hold Time

ns (min)

Data In (SI) Set-Up Time to SC (Clock) High

ns (min)

SC (Clock) Rise Time

100

ns (max)

SC (Clock) Fall Time

100

ns (max)

(1)

The LM71 will operate properly over the V+ supply voltage range of 2.65V to 5.5V.

(2)

Typicals are at TA = 25°C and represent most likely parametric norm.

(3)

Limits are ensured to AOQL (Average Outgoing Quality Level).

Figure 4. Data Output Timing Diagram

Figure 5. TRI-STATE Data Output Timing Diagram

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