PIC16F84A datasheet(28/68 Pages) MICROCHIP

28 / 68 page

PIC16F84A

DS35007A-page 28

Preliminary

6.7

Time-out Sequence and Power-down

Status Bits (TO/PD)

On power-up (Figure 6-7, Figure 6-8, Figure 6-9 and

Figure 6-10) the time-out sequence is as follows: First

PWRT time-out is invoked after a POR has expired.

Then the OST is activated. The total time-out will vary

based

oscillator

conﬁguration

and

PWRTE

conﬁguration bit status. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

TABLE 6-5

TIME-OUT IN VARIOUS

SITUATIONS

Since the time-outs occur from the POR reset pulse, if

MCLR is kept low long enough, the time-outs will

expire. Then bringing MCLR high, execution will begin

immediately (Figure 6-7). This is useful for testing

purposes or to synchronize more than one PIC16F84A

device when operating in parallel.

Table 6-6 shows the signiﬁcance of the TO and PD bits.

Table 6-3 lists the reset conditions for some special

registers, while Table 6-4 lists the reset conditions for

all the registers.

TABLE 6-6

STATUS BITS AND THEIR

SIGNIFICANCE

6.8

Interrupts

The PIC16F84A has 4 sources of interrupt:

• External interrupt RB0/INT pin

• TMR0 overﬂow interrupt

• PORTB change interrupts (pins RB7:RB4)

• Data EEPROM write complete interrupt

The interrupt control register (INTCON) records

individual interrupt requests in ﬂag bits. It also contains

the individual and global interrupt enable bits.

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. Bit GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which

re-enable interrupts.

The RB0/INT pin interrupt, the RB port change inter-

rupt and the TMR0 overﬂow interrupt ﬂags are con-

tained in the INTCON register.

When an interrupt is responded to; the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. For external interrupt events, such as the

RB0/INT pin or PORTB change interrupt, the interrupt

latency will be three to four instruction cycles. The

exact latency depends when the interrupt event occurs.

The latency is the same for both one and two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid inﬁnite interrupt requests.

FIGURE 6-11: INTERRUPT LOGIC

Oscillator

Conﬁguration

Power-up

Wake-up

from

SLEEP

PWRT

Enabled

PWRT

Disabled

XT, HS, LP

72 ms +

1024TOSC

72 ms

—

Condition

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

WDT Reset (during normal operation)

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during SLEEP or interrupt

wake-up from SLEEP

Note 1: Individual interrupt ﬂag bits are set

regardless

the

status

their

corresponding mask bit or the GIE bit.

RBIF

RBIE

T0IF

T0IE

INTF

INTE

GIE

EEIE

Wake-up

(If in SLEEP mode)

Interrupt to CPU

EEIF

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