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CS5336-TC bảng dữ liệu(PDF) 18 Page - Cirrus Logic

tên linh kiện CS5336-TC
Giải thích chi tiết về linh kiện  16-Bit, Stereo A/D Converters for Digital Audio
PDF  34 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5336-TC bảng dữ liệu(HTML) 18 Page - Cirrus Logic

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CMODE - Clock Mode Select, PIN 12.
CMODE should be tied low to select an ICLKD frequency of 256 X the output word rate.
CMODE should be tied high to select an ICLKD frequency of 384 X the output word
rate.
SMODE - Serial Interface Mode Select, PIN 13.
SMODE should be tied high to select serial interface master mode, where SCLK, FSYNC
and L/R are all outputs, generated by internal dividers operating from ICLKD. SMODE
should be tied low to select serial interface slave mode, where SCLK, FSYNC and L/R
are all inputs. In slave mode, L/R, FSYNC and SCLK need to be derived from ICLKD
using external dividers.
Digital Outputs
SDATA - Serial Data Output, PIN 16.
Audio data bits are presented MSB first, in 2’s complement format. Additional tag bits,
which indicate input overload and left/right channel data, are output immediately
following each audio data word.
DCAL - Digital Calibrate Output, PIN 9.
DCAL rises immediately upon entering the power-down state (DPD brought high). It
returns low 4096 L/R periods after leaving the power down state (DPD brought low),
indicating the end of the offset calibration cycle (which = 85.33 ms with a 12.288 MHz
ICLKD). May be connected to ACAL.
OCLKD - Digital Section Output Clock, PIN 21.
OCLKD is always 128 X the output word rate. Normally connected to ICLKA.
Digital Inputs or Outputs
SCLK - Serial Data Clock, PIN 15.
Data is clocked out on the rising edge of SCLK for the CS5336 and CS5338. Data is
clocked out on the falling edge of SCLK for the CS5339.
In master mode (SMODE high), SCLK is a continuous output clock at 64 X the output
word rate.
In slave mode (SMODE low), SCLK is an input, which requires a continuously supplied
clock at any frequency from 32 X to 128 X the output word rate (64 X is preferred).
When FSYNC is high, SCLK clocks out serial data, except for the MSB which appears on
SDATA when L/R changes.
CS5336, CS5338, CS5339
3-56
DS23F1



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