CS5336 datasheet(25/34 Pages) CIRRUS

25 / 34 page

Analog Inputs

As shown in Figure 2, the analog input signals

are connected to the CS5336 via an RC network.

R1 and C1 provide antialiasing and optimum

source impedance for the right analog input

channel while R2 and C2 do so for the left chan-

nel. The ZEROR and ZEROL inputs are tied to

the analog ground plane on the board as shipped

from the factory, but space is provided for an op-

tional RC section on each. These RC sections

may be added to model the output impedance of

the analog signal source to minimize offset error

during calibration.

Figure 3 shows the optional input buffer circuit.

This can be used as an example input buffer cir-

cuit for your application. If the ADC is driven

from a 50

Ω source impedance signal generator,

the input buffer amplifiers may be bypassed.

Place P8 and P9 jumpers in the OUT position,

and short circuit R1 and R2. This ensures that

the ADC is driven from a 50

Ω source resis-

tance. Also remove U13 op-amp, to remove the

Ω load impedance.

Timing Generator

P7 selects the master clock source supplied to

the ICLKD pin of the converter. As shipped from

the factory, P7 is set to the "INT" position to

select the 12.288 MHz clock signal provided by

U3. An external master clock signal may be con-

nected to the EXTCLKIN connector and selected

by placing P7 in the "EXT" position. Note that

R6, tied between EXTCLKIN and GND, is

available for impedance matching an external

clock source. The board is shipped with SMODE

high, which selects MASTER timing mode. In

this mode, SCLK, L/R and FSYNC are all out-

puts, generated by the converter from ICLKD.

Serial Output Interface

The serial output interface is provided by the

SDATA, SCLK, FSYNC an d L/R

B NC

connectors on the evaluation board. These out-

U13A

VA+

0.1 uF

1 k

R22

VA-

0.1 uF

1 k

R21

R1, Fig 2

U13B

1 k

R24

1 k

R23

R2, Fig 2

AINL

AINR

OUT

C32

C33

MC33078P

Figure 3. Input Buffer Circuit

CDB5336,8,9

DS23DB5

3-63

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